The present invention relates in general to input/output circuits for semiconductor devices, and more particularly to a driver circuit for driving an I/O pin of an integrated circuit.
The large scale integration of a number of devices or circuits is advantageous as it allows numerous functions to be carried out within a single integrated circuit. On the one hand, semiconductor dies or chips can be made larger to accommodate a larger number of circuits and corresponding functions. Conversely, significant improvements in lithography techniques have been achieved in order to make the existing circuits smaller so that additional circuits can be formed within a chip, without utilizing a larger-sized semiconductor chip. In order to fully utilize the functions provided by the circuits formed within the chip, I/O pins or ports are necessary. In some situations, if additional I/O pins are needed, then they are simply added to the chip as metallic pads or pins. It can be appreciated that, based on a given size of the semiconductor die, only a reasonable number of I/O pins can be accommodated. Some integrated circuits, especially those that are microprocessor-based, have more than one hundred VO pins. The I/O pins can be formed not only on the edge of the chip, but also on the planar face of the chip.
A problem exists when there are more signals or functions than corresponding pins available on the integrated circuit. One practice has been to multiplex plural signals, with respect to a single I/O pin. The multiplexing is carried out by a simple logic circuit that selects one of the signals for use with the I/O pin at any given time. An example of the use of multiplexers for coupling plural signals to a pin is set forth in U.S. Pat. No. 6,057,705. I/O pins of an integrated circuit have been utilized for both outputting digital signals via the pin, and inputting digital signals via the pin. An example of such type of input/output pin interface circuit is shown in U.S. Pat. No. 5,686,844.
In mixed signal integrated circuits, such as microprocessors integrated with A/D and D/A converters, the I/O pins must be able to accommodate not only digital signals, but also analog signals. It is a conventional practice in microcontrollers to utilize a first set of I/O pins for digital signal processing, and a second set of I/O pins for analog signal processing. This type of integrated circuit is partitioned to separate the analog and digital circuits, as well as the I/O pins,-because of the significant difference in the signal processing circuits. The digital circuits are, of course, binary operated. However, such type of circuits generate noise because of the high speed transitions of the digital signals. While the noise signals do not adversely affect digital circuits, such type of aberrations are highly undesirable in analog circuits. As such, it has been a conventional practice to not only separate the digital circuits from the analog circuits, but also maintain the analog and digital functions distinct as to the integrated circuit I/O pins. Although this limited I/O pin sharing feature provides a certain degree of flexibility, there exists other situations in which this solution is not acceptable.
From the foregoing, it can be seen that a need exists for a technique to improve the flexibility by which the various signals or functions of an integrated circuit device are made available to the I/O pins. Another need exists for a pin interface circuit that can accommodate both digital and analog signals.
In accordance with the principles and concepts of the invention, there is disclosed a pin interface circuit for use on an integrated circuit, which allows both analog and digital signals to be coupled to respective processing circuits, via a single I/O pin. In accordance with one form of the invention, the metallic pad of an I/O pin is coupled via a pin interface circuit to both analog and digital circuits formed on the semiconductor chip. The I/O pin interface is connected to the outputs of various digital circuits for driving the pin with digital signals, and connected to inputs of other digital circuits for receiving digital signals from the I/O pin. In addition, analog circuits formed on the integrated chip are connected to the I/O pin for receiving analog signals therefrom. While not employed in one embodiment of the invention, analog output circuits formed on the chip can be connected to the PO pin for driving such pin with analog signals.
When the I/O pin interface is configured for analog use, an enable signal is coupled to the digital circuits connected to the pin for disabling the same. This prevents mid-region operation by the various digital gates when the analog signals are in the mid-voltage range of operation of the digital logic. In other applications of the invention, the digital circuits may remain enabled during the analog mode of operation.
In accordance with another feature of the invention, the I/O pin interface can be configured as an output pin driven with digital or analog signals generated on the chip, and such signals can be coupled back to monitoring circuits on the chip to monitor the performance of the digital or analog signals.